Performance and Low Power Driven Floorplanning
نویسندگان
چکیده
منابع مشابه
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is important that accurate physical information is used during high-level synthesis [1]. We propose a new power optimisation algorithm for RTlevel netlists. The optimisation performs simultaneously slicingtree structure-based flo...
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Low Power Design has become a significant requirement when the CMOS technology entered the nanometer era. Multiple-Supply Voltage (MSV) is a popular and effective method for both dynamic and static power reduction while maintaining performance. Level shifters may cause area and Interconnect Length Overhead(ILO), and should be considered at both floorplanning and post-floorplanning stages. In th...
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ژورنال
عنوان ژورنال: Journal of Algorithms & Computational Technology
سال: 2007
ISSN: 1748-3026,1748-3026
DOI: 10.1260/174830107781389058